1. Field of the Invention
This invention relates generally to computer systems, and more particularly to methods for efficiently transmitting isochronous data between a computer system and a peripheral.
2. Description of the Related Art
Modern computer systems require a communication link to connect various subsystem components to other subsystem components. The various subsystem components such as a processor, memory, and input/output (I/O) devices are coupled to the bus for communication. Typically, the communication link is a bus, which includes a set of wires coupling the subsystem components and the host computer.
Buses broadly fall into two categories: parallel bus and serial bus. The parallel bus transmits a set of data bits in parallel over parallel lines. Thus, the parallel bus generally provides a fast data transfer rate. However, due to physical factors such as cross-talk, clock skew, and synchronization problems, the use of parallel bus has been limited to short distances.
On the other hand, the serial bus transmits data serially over a longer distance than the parallel bus by using a cable to communicate serial data. The serial bus is especially useful for connecting a computer system to a variety of peripheral devices that have a wide range of data bandwidth requirements. Currently several standards for serial data transmission exist, such as Ethernet, Localtalk, RS-422, Universal Serial Bus (USB), etc. Typically, these types of serial transmission systems can transmit information up to about 10 megabits per second. More recently, the computer industry has been driven toward a faster serial data transmission standard, especially in communicating with peripheral devices.
In 1995, the Institute of Electrical and Electronic Engineers (IEEE) approved a serial bus standard for a high-speed serial data transmission architecture. The standard is known as 1394-1995 IEEE Standard for a High Performance Serial Bus, which is incorporated herein by reference. The IEEE 1394 bus is often referred to as FireWire(trademark). The purpose of the 1394 standard is to provide a high-speed low cost serial bus for use as a peripheral bus or a parallel back-plane bus.
The IEEE 1394 serial bus standard provides significant advantages over conventional bus standards. One advantage of the 1394 standard is the ability to transmit data over a cable medium at variable speeds, including very high speeds. For example, transceiver chip sets for the 1394 standard are now running at speeds of up to 400 Mbps, and many companies anticipate reaching speeds of up to one Gbps (gigabits per second). The 1394 cable comes in two versions, a and b, and starts at 400 Mbps (megabits per second) to 1, and up to 1.6 Gbps. Due to its high transmission rate, the IEEE 1394 bus is projected to be the standard cable to connect high speed drives that are connected by parallel cables such as IDEs and SCSIs. The basic clock frequency of the 1394 standard is 24.576 MHz, and data is transmitted in multiples of 24.576 MHz.
Another advantage of the 1394 cable is that it allows both data and power to be transmitted such that simple, low power devices can be powered directly from the cable. To implement the dual functions of carrying data and power, the 1394 cable contains two twisted pairs of wires for carrying data signals and two additional wires for power. Furthermore, the 1394 cable can connect two components up to about 15 meters apart without a repeat assignment. In addition, it allows daisy chain connection of subsystem components.
The IEEE 1394 serial bus standard also supports a variety of protocols such as IP, ethernet, SCSI, digital audio, digital video, etc. The support for digital audio and digital video protocols, in particular, allows the IEEE 1394 serial bus to be used in communicating digital audio and/or video (A/V) data between a computer system and consumer electronic products. For example, the IEEE 1394 bus can be used to communicate digital A/V data between a host computer system and conventional consumer electronic devices such as camcorders, DVD players, CD players, digital cameras, HD TVs, etc.
FIG. 1 shows a computer system 100 including a host computer 102 coupled to a camcorder 104. Thee host computer 102 is coupled to the camcorder 104 via an IEEE 1394 serial bus 106. In this arrangement, the host computer 102 transmits digital A/V data to the camcorder 104 over the IEEE 1394 bus 106. The camcorder 104 receives the A/V data for display. Alternatively or simultaneous with displaying the A/V data, the camcorder 104 may record the received A/V data on a recording medium for storage.
The transmission of digital A/V data over the IEEE 1394 serial bus between a host computer and a peripheral electronics device is generally carried out in isochronous transactions. In isochronous transactions, a peripheral device is provided a guaranteed access to the bus at specific time intervals. Specifically, IEEE 1394 serial bus A/V devices transmit data in the form of data packets commonly known as Common Isochronous Packets (CIPs). Using these data packets, the IEEE 1394 serial bus allows a peripheral device to transmit/receive a CIP via the bus at 125 xcexcs intervals or 8,000 times per second.
FIG. 2 illustrates a structure of a CIP 200 for transmitting A/V data over an IEEE 1394 serial bus. The CIP 200 includes a CIP payload 202 and a CIP header 204. The CIP payload 202 corresponds to the payload portion of the packet that contains data defined by an application layer. On the other hand, the CIP header 204 includes various header fields including a format dependent field (FDF) 206.
The FDF 206 includes a plurality of fields. One of the fields in the FDF 206 is a synchronization time (SYT) field 106. The SYT field 106 in the CIP header 104 is used to store a presentation time stamp for the associated CIP 200. The presentation time specifies the time at which to present the packet data for display in the case of a video data or for play in the case of an audio data.
The IEEE 1394 serial bus is often used in computer systems that operate under an operating system, (e.g., Microsoft(copyright) Windows 95(copyright), Windows 98(copyright), and the like), which may provide preemptive multitasking environment. In such an environment, transmission of CIP based data from a host computer to a peripheral A/V device may present several problems due to the real time requirements of A/V protocols. More specifically, the A/V protocols were originally specified to facilitate transfer of A/V data between consumer electronic devices such as VCRs, TVs, camcorders, and the like. These consumer devices typically include a micro-controller that provides the customized hardware support for the A/V protocols. For instance, the micro-controllers provide time-stamp, synchronization, and other support for the real time transmission and presentation of A/V data.
Within a computer system, however, the real time A/V data processing requires substantial processor time to set up and transmit CIPs. For example, in a preemptive multitasking environment, the host computer typically computes and creates a presentation time in advance of the transmission of a data packet. On the receiving end, the A/V devices generally include a high-resolution timer, which allows creation and attachment of SYT field data on-the-fly. For proper synchronization, the host computer adjusts the presentation time during the transmission of a series of CIP data packets to ensure that it matches the data rate expected by an A/V device receiving the data packets. In general, the transmission rate of the full CIP data packets exceeds the expected data rate. Hence, if the presentation time of the SYT field 106 is not properly matched with the expected data rate, the A/V device may exhibit jitter during the display of video data or during the play of audio data.
To reduce such jitter effect, conventional techniques have sought to match the transmission data rate with the expected data rate. To that end, these approaches have typically adjusted the presentation time by creating and inserting empty CIPs from within a preemptive multitasking environment. The creation and insertion of the empty CIPs had the effect of reducing the transmission data rate down to the rate expected by the A/V device.
Conventional computer systems have implemented these matching techniques by creating and modifying direct memory access (DMA) script programs to transmit both empty and non-empty CIPs. FIG. 3 illustrates a flowchart of a conventional method for creating DMA script programs for transmitting CIP data packets. The method begins in operation 302 and proceeds to operation 304, where buffers are initially filled with A/V data. Then in operation 306, CIP headers and SYT field values are created and inserted into the buffers that are arranged in a linear fashion. Next in operation 308, empty CIPs for the initial data buffers are calculated and inserted into the buffers. Operation 308 completes initial setup stage.
After the initial setup stage, a linear DMA script program describing full and empty CIPs are created in operation 310. Then, the linear DMA script program is, in operation 312, started on a particular cycle. In operation 314, the initial data buffers are detached and new data buffers are attached (i.e., allocated) on-the-fly. Next, CIP headers and SYT field values are created and inserted into the newly attached buffers on-the-fly in operation 316. Then in operation 318, a new linear DMA script program is created and dynamically appended on-the-fly. This process continues until all desired A/V data have been transmitted. The method then terminates in operation 320.
While this method of creating DMA script programs to transmit CIP based data produces reasonable results, it utilizes significant processor resources. This is because a processor must create the script program many cycles in advance of execution in order to overcome operating system latencies. More specifically, the calculations, adjustments, and creation of SYT field value and the empty CIPs must be done on-the-fly by the CPU many cycles in advance of transmission of CIPs. Such processing requirements generally result in a very large and complex DMA script programs.
Furthermore, these DMA script programs were usually generated and modified in a linear fashion so that the DMA script programs were very lengthy. Such lengthy and complex DMA script programs generally require a greater CPU utilization, thereby reducing the availability of the CPU for other devices or subsystems in a computer system. In addition, the presentation time in the SYT field of the conventional method tended to drift away from the expected data rate with time. This drift in SYT value is typically caused by some missed or lost isochronous cycles.
Thus, what is needed is a method and system for efficiently transmitting isochronous A/V data packets without significant processor utilization. In addition, what is also needed is a method and system that can efficiently generate and adjust SYT field values and empty CIPs.
The present invention fills these needs by providing methods and system for isochronously transporting audio and/or video (A/V) data in common isochronous packets (CIPs) over a serial bus. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium.
In one embodiment, the present invention provides a method for isochronously transporting A/V data in CIPs over a serial bus. A memory space is allocated for a set of buffers to store a plurality of CIPs. Each of the CIPs includes a header field and a data field with the header field having a synchronization time (SYT) field for storing a presentation time. Initial CIP header values are generated including initial SYT field values for each of the CIP header fields in the set of buffers. A circular DMA script program is generated and configured to describe a set of full and empty CIPs for each of the buffers. The circular DMA script program is configured to transmit the CIPs from the buffers. The generated DMA script program is executed to sequentially transmit the CIPs from the buffers by traversing the buffers in a circular manner so that the transmitted CIPs are presented at the associated presentation time. The DMA script program generates an interrupt periodically to copy new CIP data into the CIP fields of buffers from which the CIPs have been transmitted such that the new CIP data including new SYT field values are set up for transmission in advance.
In another embodiment, the present invention provides a computer system for isochronously transporting A/V data in CIPs over a serial bus. The system includes a bus, a main memory, a processor, and a host interface. The main memory is coupled to a bus and is configured as a set of buffers to store a plurality of CIPs. Each of the CIPs includes a header field and a data field. The header field has a SYT field for storing a presentation time. The processor is coupled to the bus to generate initial CIP header values including initial SYT field values for each of the CIP header fields in the set of buffers. The processor generates a circular DMA script program that describes a set of full and empty CIPs for each of the buffers, the circular DMA script program being configured to transmit the CIPs from the buffers. The host interface is coupled to the bus and includes a host link device and a PHY device. The host interface being configured to receive and transmit the CIPs from the buffers to a peripheral device over the serial bus for presentation at the associated presentation times.
In yet another embodiment, the present invention provides a method for isochronously transporting A/V data in CIPs over a serial bus. Each CIP includes a header field and a data field. The header, in turn, includes a SYT field for storing a presentation time. The method includes: (a) copying CIP data into a set of CIP data fields; (b) generating CIP header values including SYT field values for each of the CIP header fields; (c) describing a set of full and empty CIPs for each of the CIPs for transmission over the serial bus; (d) sequentially transmitting the CIPs from a first CIP to a last CIP; (e) periodically generating an interrupt to copy new CIP data into the CIP fields from which the CIPs have been transmitted such that the new CIP data including new SYT field values are set up for transmission in advance; and (f) repeating the operation e) by looping from the last CIP to the first CIP when the last CIP has been transmitted.
The present invention advantageously provides a method and system for transmitting isochronous CIP data packets without substantial processor involvement. In particular, by reusing a generated DMA script program, the processor is freed from the highly processor-intensive task of repeatedly generating DMA script programs to transmit new CIP data packets. These and other advantages of the present invention will become apparent to those skilled in the art upon a study of the specification and drawings describing the present invention.